Design-Reuse

Axi dma micro dma IP Listing

The Digital Blocks DB-DMAC-MC2-DL-MM2S-S2MM Verilog RTL IP Core is a Multi-Channel Scatter-Gather DMA Controller that transfers data between AXI4 Memory Map and AXI4-Stream Interfaces. Control ... The ...
Business Wire

PLDA Announces Two Innovative vDMA Engine IP Solutions, Delivering Robust Performance and Scalability across a PCIe Link or AMBA AXI Fabric

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in PCI Express® IP solutions, today announced two innovative DMA engine solutions designed to manage large and heterogeneous data traffic ...
EDN

PCI Express Endpoint-DMA Initiator Subsystem

This application note demonstrates several key features of the Vivado Design Suite and the IP cores used in the design. The key features that are illustrated by this design include: Each of these ...
EDN

AXI VDMA Reference Design

This application note demonstrates the creation of video systems by using Xilinx native video IP cores such as AXI Video Direct Memory Access (VDMA), Video Timing Controller (VTC), test pattern ...
Design-Reuse

PLDA Announces Two Innovative vDMA Engine IP Solutions, Delivering Robust Performance and Scalability across a PCIe link or AMBA AXI fabric

New solutions provide scalability, low resource utilization and high performances in managing large amounts of data for designers and architects in the high-end computing, AI, machine learning and IoT ...